1. Technical Field
The present invention relates to a semiconductor memory device and, more particularly, to a data read path that increases data read speed and lowers power consumption in the semiconductor memory device.
2. Discussion of the Related Art
FIG. 1 is a block diagram illustrating a data read path of a memory cell in a conventional semiconductor memory device. In the conventional semiconductor memory device of FIG. 1, the same internal power voltage (hereinafter, referred to as “IVC”) is supplied to the whole data read path, which amplifies data of a memory cell (not shown) and reads it. The data read path includes a first MUX 10, an input/output sense amplifier (hereinafter, referred to as “IOSA”) 20, a second MUX 30, an output buffer circuit 40, an output driver circuit 50, and an internal power supply circuit 60. During a data read operation, data of the memory cell is outputted to a global line pair GIO and GIOB, passes through the first MUX 10 and is amplified in the IOSA 20. The data amplified in the IOSA 20 is converted to data having an appropriate bit organization in the second MUX 30. The data is outputted to an external terminal through the output buffer circuit 40 and the output driver circuit 50. The output buffer circuit 40 controls the output driver circuit 50. As described above, since the data of the memory cell goes through many circuit components until it reaches an output terminal, a predetermined delay time is incurred before the data is outputted.
Therefore, when a semiconductor memory device is used in a system requiring a high operation frequency, a need exists for a method and apparatus that reduces the delay time tAA caused by various circuit components before the data is outputted.
One conventional method for reducing the delay time tAA is by increasing the IVC level of the whole data read path to improve both data read speed and current driving abilities of transistors that constitute the circuit placed on the path.
FIG. 2 is a block diagram illustrating a data read path of a memory cell with circuit components that have improved operation speed when a voltage supplied to the data read path is increased by a predetermined level. Referring to FIG. 2, the data read path includes a first MUX 10, an input/output sense amplifier (hereinafter, referred to as “IOSA”) 20, a second MUX 30, an output buffer circuit 40, an output driver circuit 50, and an internal power supply circuit 60. The data read operation illustrated in FIG. 2 is similar to the operation described in FIG. 1 except that there is an increase of data transmission speed in respective circuit components. In detail, FIG. 2 shows the different percentages that the data transmission rate in respective circuit components is improved when the IVC supplied from the internal power supply circuit 60 is increased by Va (For example, 0.1 volts˜0.2 volts). Assuming that the overall percentage of improvement of an operation speed of all circuit components placed on the data read path is 100%, FIG. 2 shows that the IOSA 20 is improved by 63%, the second MUX 30 is improved by 12%, the output buffer circuit 40 is improved by 10%, and the output driver circuit 50 is improved by 15%.
As shown in FIG. 2, when the IVC supplied from the internal power supply circuit 60 is increased by Va (e.g., 0.1 volts˜0.2 volts), among all circuit components placed on the data read path, an improved percentage of an operation speed of the IOSA 20 reaches about 63%. Therefore, if only the power voltage supplied to the IOSA 20 is increased, without increasing the power voltage of other circuit components placed on the data read path, the data read speed should have similar increases as to the increases resulted when the power voltage is supplied to all of the circuit components.
However, the method of increasing the power voltage supplied to all circuit components on the data read path increases the operation current of the semiconductor memory. Further, the second MUX 30 performs a bit organization of data transmitted through the data read path, the output buffer circuit 40 is synchronized with a clock signal to output data to the output driver circuit, and the output driver circuit 50 outputs data to an external terminal. The aforementioned three circuit components draw an increased amount of current if the applied voltage is increased and thereby increase power consumption. A need therefore exists for a semiconductor memory device having a data read speed with minimal delay and power consumption.